The Node is made up of mainly five blocks,
1.DATA INPUT LINK
2.RESULT OUTPUT LINK
3.CODE, STATUS & PARAMETER LINK
4.WORK-SPACE MEMORY
1.Data input link :
The input data are available for the DSP node from a memory located on the program memory ( PM ) side. The data flowing from the polarimeter get written into this memory at a steady speed, while the processor reads them out as and when required by the processing algorithm. Since the data flow from the polarimeter to the DSP node is unidirectional and the input rate and the processing rates are different, this memory size is chosen to buffer the data sufficiently ( 32-bit X 32K FIFO block ). The write port of the FIFO block is interfaced to the polarimeter and the read side is connected to the DSP node. The Stokes parameter data form 32-bit inputs ( 4 X 8-bit, 2's complement format ), and data of 32 frequency channels are written sequentially into the FIFOs. A formatting logic sign-extends the 8-bit numbers of each stoke parameter to a 32-bit, fixed point, 2's complement number, to match the DSP data bus-width. In doing so, the address of the four FIFOs corresponding to the four Stokes parameters are organised as separate pages, so that consecutive reads procure consecutive Stokes parameters. In this way, the FIFO depth is exploited to provide maximum buffering. The format conversion logic is an add-on card. An alternate, pin-compatible bypass logic has been developed to use the 32-bit as a single, unaltered word sequence, to provide for other applications.
2.Output link :
The processed results in one of the two logical partitions of the work-space memory are copied into a 32-bit X 32K FIFO module designed as OP_FIFO. The input of the OP_FIFO is mapped onto the DM side of the DSP chip. This allows that simultaneously results can be transferred into FIFO, while previous results in the FIFO can be read out from all nodes for storage. The OP_FIFO outputs of all nodes are connected to a common output bus and are sequentially read-out under the control of the DAS.
3.Code, Parameter and status link :
The parameters required for processing ( such as the correction factors for Faraday rotation, Doppler acceleration, etc ) are supplied to the DSP from a separate memory on its program-memory ( PM ) bus. The instruction code for the DSP node is also located in this memory. It will be necessary to update the process parameters on-line, without disturbing the processing in the DSP node. it will be convenient to have a common control block for all DSP nodes from which the instruction code and process parameters can be down-loaded and updated on-line. The controller must be able to read back and check what it has written into its memory, before letting the DSP use it. The controller-DSP node communication protocol requires many semaphores. These semaphores may be bi-directional and are also located in the same memory for simplicity. A 48-bit X 8K, dual port RAM block is chosen to hold the instructions, parameters and semaphores. One port of the DPRAM is connected to the controller, while the other is interfaced to the PM side of the DSP node. The DPRAM has 25ns cycle time, to allow zero-wait-state access from the DSP and STOKEGEN. Two 32-bit, memory mapped ports on the DM side of the DSP node bring all status flags to the code bus in each node, which can be polled during processing.
4.Work-space memory :
A scratch-pad memory holds the temporary results during the processing of the data. This is organised as 32-bit X 512 K SRAMs, ( 25ns access time ) and is interfaced to the data memory ( DM ) side of the DSP node. This memory is logically organised into two halves ( banks ). One half is used for processing and after the processing is complete for one set of data, the second half is used for processing the next set of data. Meanwhile, the result can be read out from the first half, so as to empty the first half before the processing in the second bank is complete. then the processing is done on a fresh data set in the first half while the results in the second half are transferred. Physically, this memory is organised as two memory chip-modules, and can be upgraded to contain upto 32M X 32-bit.