I design FPGA-based digital signal processing systems for GMRT (Giant Metrewave Radio Telescope). Currently, I am working on developing radio frequency interference mitigation algorithms for the upgraded GMRT project and a multi-beam beamformer for the Expanded GMRT project. My work in these projects started from algorithm development, simulation, implementation, testing and data analysis. I use some of the latest simulation tools and signal processing platforms (like Xilinx RF System-on-chip) in these projects. In the past, I have worked on model-based design of FPGA blocks for correlator system. This work was done to build subsystems for FPGA-based signal processing chain and as part of the CASPER collaboration. I am a co-investigator in the current plan proposals for the digital backend for upgraded GMRT and the Expanded GMRT. A list of the student projects guided by me is available at the end of this page.
Real-time Radio Frequency Interference (RFI) Mitigation for the GMRT Wideband Backend (GWB)
Manmade RFI is the one of the primary reasons for reduction in the sensitivity of a wide-band radio telescope. Various techniques have been proposed over the years for mitigating RFI. Most of these contemporary techniques are implemented in the digital subsystem of the radio telescope receiver. In the digital domain, it is advantageous to mitigate RFI at the highest possible time resolution (theoretically at the Nyquist rate). More details on RFI and contemporary techniques for mitigation of RFI are described in this paper.
At GMRT, the lower radio frequencies (up to 800 MHz) suffer from impulsive (broadband) RFI which is primarily generated from sparking and corona discharge on high-tension powerlines around the array. To mitigate the effects of this interference, we have built a real-time RFI excision system detects the RFI and filters it. The detection is based on computation the signal dispersion using Median Absolute Deviation (MAD) estimator. The challenge has been to implement MAD-based filtering technique in real-time (at 800 MHz sampling rate) on FPGA. After a series of tests, we came up with a more robust estimation using Median-of-MAD (MoM). Several new test techniques were developed to test the real-time RFI filtering and its effects on astronomical data. After rigorous testing for more than two years, the technique is now fine-tuned to provide the best performance for broadband powerline RFI excision.
We have also developed analog instrument to emulate the broadband and narrowband RFI. This is being used for carrying out controlled experiments to characterize the algorithm. As part of the engineering tests, we have explored various parameters of astronomical significance like the cross-correlation function, closure phase and phase of the cross-correlation.
This system is a part of the GWB and is available for use during the observations with the Upgraded GMRT. Here is a document for GMRT users wanting to use it during their observations.
A brief overview of the design and results (2014 version) is provided in the following link on the CASPER website. Presentation from a recent talk summarizes the current status and latest developments.
Multi-element Multi-beam Focal Plane Array Beamformer Development
Focal plane array (FPA) beamforming is being developed for the Expanded GMRT project. I am supervising the development of FPGA-based wideband correlator and multi-beam beamformer. A prototype beamformer has been developed for 32-input, 32 MHz, 1024 spectral channels and 5 independent beams on ROACH-1 board (Xilinx Virtex-5 FPGA). The beamformer is being tested in the free-space test range at GMRT. We use the L-band (1.1 - 1.7 GHz) FPA procured from ASTRON for testing the beamformers. Currently, we are operating the focal plane array in the aperture array mode and work is going on to achieve optimum SNR using beamforming algorithms.
In parallel, we are developing wideband beamformer with 300 MHz bandwidth and multiple beams using Xilinx RF System-on-Chip (RFSoC). The end-to-end system-level simulation of the antenna, RF and digital beamforming system is being carried out using MATLAB's Antenna Toolbox and Simulink.
Presentation from a recent talk summarizes the current status and latest developments.
Subsystems developed for the GMRT correlator/beamformer and CASPER collaboration
The subsystems developed by me are variable-correlation digital noise source, single and multiple-board (packetized) FPGA-based coherent and incoherent beamformer (for pulsar observations, time-domain astronomy). The designs are optimized at the architectural and implementation level for area and timing performance (mostly for Virtex-5 FPGA) on ROACH-1 board from CASPER. Testing of these designs is carried out using the GMRT wideband backend (GWB) receiver chain. These blocks have been verified and contribute towards development of signal processing hardware for the open-source collaboration CASPER (Collaboration of Astronomical Signal Processing and Research). CASPER promotes open-source hardware, software and programming tools, which can be collectively developed by the community and re-used in multiple experiments to best leverage the cost and time of development. The collaboration and its work are summarized through this poster and paper.
FPGA-based Variable Correlation Digital Noise Source
A digital noise source is useful for testing signal processing designs in a radio telescope backend. A digital noise source generating a Gaussian distributed data can be implemented on FPGA along with the other signal processing blocks forming a correlator or a beamformer subsystem. FPGA based low foot print digital noise source was developed and tested at the GMRT. This noise source has been used to verify & debug wide-bandwidth correlator designs for the GMRT wideband system. The design is available as a CASPER library block and a memo on the CASPER website gives design details of this block.
FPGA-based Wideband Beamfomer Designs
Array beamforming is used for improving the sensitivity of the radio telescope receiver. This mode is used for observing and searching pulsars. A 300 MHz bandwidth, 512 spectral channel, single ROACH-1 board (Xilinx Virtex-5 FPGA) beamformer was designed with 4 inputs. The incoherent beamformer design called Pocket Beamformer (PoBe) was tested with the GMRT receiver system with test inputs and radio source (pulsar). The details of the design and test results are available in this memo . A single board coherent beamformer has been developed. This includes a correlator for computing the phase of the cross-correlation pairs and phasing the array inputs prior to beamforming.
Further, an 8-input 400-MHz beamfomer was developed using the packetized correlator concept (i.e. a set of FPGA boards performing the Fourier Transformation and delay correction operation while the other set performing correlation, beamforming and accumulation operations. Boards are inter-connected through a 10 Gigabit Ethernet interface.). This design was tested with the wideband signal receiver chain, details of which are described in this memo .
10 Gigabit Ethernet: CX4 to SFP+ adapter - System Design and Testing
The main function of this adapter board is to serialize data arriving at a speed of 3.125 Gbps over four lanes into a single 10 Gbps lane. ROACH-1 board from the CASPER collaboration is used at GMRT for real-time signal processing. This board is equipped with four CX4 connectors. Each connector receives four lanes from ROACH board FPGA (Virtex-5). The widely accepted standard for 10GbE data transfer over copper or fiber is changing to the SFP+ (Small Form-Factor Pluggable). As the industry moves toward the SFP+ standard, large port switches with the CX4 connectors are getting obsolete. For a ROACH-based packetized digital backend system, to process data from an array of antennas, an adapter board capable of converting CX4 standard to SFP+ standard is necessary. This board was conceptualized by GMRT backend team and was jointly developed by GMRT and MTE (Pune).
The details of the project are provided on this link. Subsequent to this project, a standalone unit for CX4 to SFP+ conversion was designed at developed and the details on the unit are described in the poster presented at the CASPER 2012 workshop.
Students supervised under the GMRT Student Training Program (STP)
NCRA-GMRT runs short and long term student technical training program. The short term programs are mainly during the summer and are meant for students in their pre-final year of diploma, graduation, or post-graduation. The long term program runs follows the academic calendar and is meant for final year students. STP students work on engineering projects related to development and upgrade of the GMRT. For more details visit this link.
The list of students guided or co-guided by me on various projects related to digital signal processing and backend systems is available here.
Projects before joining GMRT
I worked with eInfochips Ltd. at Ahmedabad from April 2005 to August 2009 as ASIC Engineer. eInfochips is a semiconductor design services company. Here I worked on projects related to Digital Design, RTL coding using Verilog HDL and VHDL, FPGA-based System-on-Chip (SoC) architecture and ASIC Intellectual Property (IP) core design, documentation (SRS, Functional and Design specifications, Verification Environment and Comprehensive Test Plan), RTL synthesis and static timing analysis for FPGA and ASIC designs, functional and gate level verification of FPGA/ASIC/SoC designs. I have worked on various projects outsourced to eInfochips from various semiconductor giants.
A partial list of projects executed successfully are high-speed video data transfer applications, USB mass storage device, hard disc read channel, video switch matrix and ASIC/FPGA IP cores (SPI 4.2, DDR2 Memory Controller,I2C bus, BT.656 video interface, NAND Flash memory controller, DMA controller).