Eight sets of four dish sums, thus obtained are available to the Eight Input Cards ( EIC ) for further addition. There are 3 identical Eight Input Cards handling the Power, Real & Imaginary term separeltely. The basic function of this card are given below :
Accepts the four dish sum terms from the Eight four input cards.
Sum all te 8 terms.
Demultiplexed the polarisation Channels.
Hardware Details :
There are Eight power, real-imaginary terms each 8,7,7-bits wide, at the 8-input cards ( EIC ) for summing. All these 3 cards have identical hardware circuits, but are programmed to perform simple addition in the case of power, and 2's complement addition for the real and imaginary terms. One of the card is described here. The details are given here.
The input data enters the first stage clearable ( 74FCT162823 SMD ). All of the 8-inputs may not be present during the operation, hence a masking provision is available to exclude any given set of inputs in the summing. The register clear signals are coming from the Card Enable register ( U43 ). The control computer configures the Card Enable register. The data outputs from these registers are fed to teh next stage of the binary network ( first adder stage in this card ) for further addition.
The addition of 8 inputs can be carried out in 3 levels using the binary tree network. For this purpose it is required to have 8, 9, 10-bit wide adders corresponding to teh three levels. Due to hardware implementation considerations, eaach of these adders are split into two pipeline stages ( postponed carry addition ) and implemented in the EIC.
1.Third Level Addition( 8-bit adders ) :
The inputs are 8-bits each, and there are 8 of them.
Pipeline-1 adds the successive two least significant 6-bits and produces 7-bit outputs. There are four such adders implemented in four EPROMs ( CY7C264 ) to cater to the 8-inputs. The results are latched and forwwarded to pipeline-2.
Pipeline-2 adds the two most significant 2-bits along with the corresponding carry produced in the previous pipeline. These are implemented as four numbers of 2, 2, 1-bit adders. Two such adders are implemented in one EPROM ( CY7C291 ). There are two such EPROMs.
The final sums here, are four 9-bit wide numbers. These outputs are available for teh second addition.
2.Fourth Level Addition ( 9-bit adders ):
The inputs for this stage are four 9-bit numbers from the previous stage. Pipeline-1 adds the successive two least significant 6-bits and produces the 7-bit outputs. There are two such adders at this stage, they are implemented in two EPROMs ( CY7C264 ). The results are latched and forwarded to pipeline-2. Pipeline-2 adds the remaining successive two most significant 3-bits along with the corresponding carry produced in the previous pipeline. These are implemented as two numbers of 3, 3, 1-bit adders. Each adder is implemented in one EPROM ( CY7C291 ). Here, there are two outpts, each 10-bits wide.
3.Fifth Level Addition ( 10-bit adder ):
The inputs for this stage are two 10-bit numbers from the previous stage. Pipeine-1 adds the two least significant 6-bits and produces the 7-bit output. The adder is implemented using an EPROM ( CY7C264 ). The esult is latched and forwarded to the next pipeline. Pipeline-2 adds the two most significant 4-bits along with the carry produced in the previous pipeline. This is implemented as a 4, 4, 1-bit adder. It is implemented in one EPROM ( CY7C291 ). Here, the 2-inputs are added together to produce a 11-bit output.
Sub-Group :One of the inputs to this stage ( sum of data from dish 1 to 16 ) is brought out as a sub-group output. The main summing stage is also optionally bypassed to produce the second input of the adder ( sum of data from channels / dish 16 to 32 [ : there are 32 inputs to the summing hardware ] ) as another sub-group. The data output from both these groups are format converted, demultiplexed and are available to the back-end instruments. The hardware implementation of this will be discussed in detail.
4.Output Format Control:
The sum output after the last stage addition is fed as lower 11 address bits ( lower 10-bits in the case of sub-group outputs; where the eleventh address bit is grounded ) of the Format-control EPROM. The upper three address bits of the EPROM are supplied from a Format Select register ( U47 ). These 3-bits can select upto 8 different formats. This Format Select register is configured by th econtrol computer. The output data corresponding to the selected format will appear with a maximum data size of 11-bits ( 10-bits in the case of sub-group outputs ).
Since the real, imaginary terms are combined in independent cards, they have separate Format-Output sections. However care must be taken in the control software to handle them identically.
Sub-Group :
The sub-group outputs, the representing the sum of 4-input-card-0 to card-3 sum outputs, are available. The outputs, are 10-bits wide. The main group output can be programmed to give either the full sum of all the 4 input card outputs ( dish 1 to 30 ) or bypass the addition and give only the sum belonging to the second group, i.e. card 5 to 7. This bypass mode is activated by setting the M0 bit in the SubGroup / PolEnable register ( U45 ). This M0 bit forms an additional ( address ) input to the 10-bit adder stage ( Last level ) EPROMS ( U25, U33 ) and configures them to work in Adder or the 10-bit adder stage ( last level ) EPROMS ( U25, U33 ) and configures them to work in Adder or By-pass mode.
5.De-multiplexer :
Now the formatted data enters the de-multiplexer stage. The two phase clocks ( CK1 and CK2 ) coming from the Clock Control section demultiplexes the data. The data which appears for the even clocks are latched by CK1 and the odd ones by CK2. After de-multiplexing the Polarisation-1 data appears first and Polarisation-2 data one clock later. This delay differences are compensated by, again latching the polarisation-1 data using CK2 clock. The two polarisation channels will have a data rate of 16MHz per channel.