The G.M.R.T. Array Combiner ( GAC ) can be broadly divided into these subsections :
1.The ECL to TTL Section :
The complex spectral data are coming from the FFT as ECL differential signals. These are inputs corresponding to data from 30 FFT modules. These signals are converted to TTL levels, latched and forwarded to the Input Conversion state.
2.Input Conversion Section :
The mantissa exponent format complex numbers entering this block are converted to the corresponding power, a linear format real, imaginary terms. The conversion is carried out by using EPROM based look-up tables. The power terms produced are 6-bits wide and real, imaginary are 5, 5-bit wide. The EPROMs contain two banks of 16 tables suitable for measuring different input signal ranges. Presently one of the bank is used for storing the diagnostic signals. The bank selection is activated by programming a control register. The range control bits are coming from the gain RAMs selects one of the 16 tables in a given bank. The pain control bits are commonly available to both IA and PA tables ( power, real, imaginary sections ).
3.Gain Control Section:
A 4-bit wide R/W RAM ( one RAM per dish ) addressed by channel counter ( 10bit wide ) supplies the range control bits to the input conversion sections. Contents of the RAMs are loaded from control computer. This gain control feature is available to all the 30 dish inputs, the two polarisations and for the individual spectral channels.
4.Combiner Network Section :
The Combiner network combines the 30 inputs ( power, real, imaginary ) using a 5 level binary adder network. There are 3 identical networks meant for summing the power, real, imaginary terms. The adder network for the power terms is configured to add positive numbers and the real, imaginary networks are configured to perform the 2's compliment addition. The entire network is implemented using suitable high speed EPROMs in multiple pipe-lines stages.
The first two levels of binary networks ( 6, 7-bit adders ) are implemented in pipe-line stages ( one pipe-line per level ). The last three levels ( 8, 9, 10-bit adders ) are implemented in 6 pipe-line stages ( 2 pipe-lines per level ). The hardware up to the second level addition are implemented in the 8 identical boards. The antenna masking provision is provided at the inputs of the first level adder itself. Selective inclusion or masking of any combinations of antenna inputs are possible at this level. There are separate masking provisions are available for IA and PA networks.
Another additional stages of masking is provided at the inputs of the three level adder. From this level hardware is implemented in another set of 3 identical cards. At this stage onwards, the summation of power, real and the imaginary terms are carried out in separate card. The masking provision helps in avoiding any set of inputs for further addition if the corresponding previous stage cards are not present.
5.Format Control Section:
The final sum output data format can be suitably altered to match to the requirements of the back-end instruments. The format conversion section is implemented using an EPROM. This section accommodates upto 8 formats with a maximum data size of 11-bits. Suitable data scaling is also provided at this stage.
6.Sub-Group Facility:
A provision is available to bring summed outputs corresponding to two independent groups to the back-end instruments to facilitate sub-array observations. In this, each group can have a maximum of 16 dishes. These are the partial sums from the network tapped out before performing the last level addition. This provision is available for both the IA and PA mode outputs.
7.Demultiplexer Section:
The Array Combiner processes the time-multiplexed 2-polarisation channels. They are separated ( demultiplexed ) into individual the sub-group outputs are demultiplexed to produce a corresponding polarisation 1 and 2 channels with a reduced data rate of 16MHz.
8.TTL to ECL Section:
These are buffer driver stages, facilitating proper distribution of the array combiner outputs to the different back-end instruments. The TTL outputs from the array combiner are converted to ECL differential signals and distributed using twisted pair cable.
9.Control Computer:
The Array Combiner operating parameters ( mask registers, gain values, etc. ) are loaded from a control computer, which also monitors the system status during the operation. A control software gives the user interface to the Array Combiner system.
The following cards are used in the G.M.R.T. Array Combiner ( GAC ) :
1.4 Input Card
2.8 Input Card
3.Buffer Card
4.Clock Card
5.Backplane
6.Distribution Card