This card receives the basic CLOCK and INIT signals from the external MASTER system. It further precesses the clock and INIT signals and redistributes to the rest of the GAC system and hence to th enack-ends.
1.Analog CLOCK Section:
The Clock Card has provisions to receive the basic clock either in the form of Sine wave or ECL differential. Currently the sine wave mode is used. Sine Wave Clock is received through SMA1 connector. U1-AD9617 acts as a buffer cum ECL level shifter. VBB from U2 is applied across R5 ( 5K ) POT, and the reference for AD9617 is obtained. POT R3 ( 5K ) and POT R2 ( 5K ) can be used to adjust the gain. U1A-MC10116 acts as a schmitt ECL buffer which keeps the clock free from noise. At U3A-MC10125 output the sine wave get converted to TTL levels.
2.INIT and SEQUENCER Section:
The Clock Card has a PROM based sequencer, which helps to synchronise the GAC channel counters with the FFT first data channel. The INIT signal is used for this purpose. The INIT is expected to come from the external MASTER CLOCK generator. It is a ECL Differential Signal. This signal should come atleast once in the beginning, and can repeat once every integral multiple of the FFT cycles ( 516 FFT cycles ). The PROM contents can be programmed to generate the interna INITs for GAC for with an appropriate delay after the arrival of the external INIT. A C-program is used to generate the contents of the sequencer PROM. The CLOCK and INIT signals can be delayed ( using delay modules U4 and U10 respectively ), as soon as they enter the board and are converted to TTL levels. Then the INIT and the Clock are synchronised by capturing the INIT with the clock in a flip-flop ( U12A ). To capture INIT is conditioned with the INIT generated from the PROM ( PR ) at U11A to produce the reset signal ( SR ) for the counters in the Sequencer section. The U11A allows the external INIT also to, reset the counters, whenever it arrives. Thus facilitating a re-synchronisation possible.
3.GAC-ON Generate Section :
The GAC-ON is a signal available to the back-end systems to know the availability of the GAC for use. This signal status is generated by teh flip-flop logic ( U22A, U22B and U18 ) available in the clock-card. The CS11 and CS12 are the two card select signals, that come to this board from the Control-PC set or reset these flip-flops to generate the GAC-ON signal as true or false.
4.LED Section:
The LED section is used to indicate the presenceof the external INIT and teh CLCOK, by the flickering of the two LEDs in the circuits. Each of these LEDs in the circuit. Each of these LEDs are driven by a dual monostable multivibrators circuit with INIT and clock being their respective trigger inputs.
5.SPARE Sequencer and General Purpose Section :
A spare Sequencer PROM and its output buffers ( U19 and U20 ) are provided. This can be used to generate any additional control signals or for any other future use. A special section consisting of U23 and JP12 are provided to meet any additional clock and INIT output requirements in future. This can also be used to send clock and INIT to any bsck-end system through JP12. The U9C-MC10125 can be used to receive the basic clock or any other signal inthe ECL differential from through JP7.