The error detection uses both Cyclic Redundancy Check (CRC) and checksum methods. SDLC/HDLC supports 16 bit CRC error detection. CRC can detect all the single errors, double errors and burst errors up to 16 bits in length and can also detect 99% of burst errors of lengths greater than 16 bits.
The way this works is as follows. A cyclic code message consists of a specific number of data bits and a Block Check Character (BCC). Let equal the total number of bits in the message, equal the number of data bits, i.e. is the number of bits in the BCC. The code message is derived from two polynomials which are algebraic representations of two binary words, the generator polynomial and the message polynomial . The generator polynomial is a type of code used in CRC-12, CRC-16 and CRC-CCITT.
For example, bits of binary data can be represented as a message
polynomial of degree . Thus, an eight-bit long message
is represented as
(24.3.1) |
The code message can be constructed as follows:
The division is performed in binary without carries or borrows. The code message is transmitted as binary data and the receiver at the other end retrieves the message using the same generator polynomial and accepts the data if the remainder is zero.